1. Field of the Invention
The present invention relates generally to a system and method for providing an interface between an Ethernet physical media interface (PHY) and a Media Access Controller (MAC). More specifically, the present invention relates to an interface that accommodates a PHY with a lower data rate than the MAC.
2. Relationship to the Related Art
In computer network systems there is typically a natural division between chips handling the physical layer, which is responsible for transmitting data on the network, and the system chips, which perform logical operations with data transmitted on the network. Ethernet hubs, routers and switches are composed of multiple ports, and may be generically referred to as multi-port Ethernet devices. Each port is typically composed of a system chip, which includes a media access controller (“MAC”) layer, and a physical layer or “PHY.” Modern multi-port Ethernet devices typically integrate multiple MACs into one system chip (MAC chip) as well as multiple PHYs into another chip (PHY chip). An interface is required on each chip to transfer signals between the MACs and the PHYs.
IEEE Standard for Information technology—Telecommunications and information exchange between systems—Local and metropolitan area networks—Specific requirements, Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications, IEEE Std 802.3™-2005, provides a standard for Ethernet local area network operation including interfaces between the MACs and the PHYs.
Section 4 of Part 3 of IEEE Std 802.3™-2005 provides for a 10 Gigabit/second (Gb/s) baseband network and connection of a 10 Gb/s capable MAC to a 10 Gb/s PHY. Interfaces that can connect a 10 Gb/s capable MAC to a 10 Gb/s PHY include 10 Gigabit Media Independent Interface (XGMII), 10 Gigabit Attachment Unit Interface (XAUI), 10 Gigabit Sixteen-Bit Interface (XSBI), and the high speed serial electrical interface for 10 Gb/s small form-factor pluggable transceiver (XFP) modules (XFI).
FIG. 4 is a block diagram illustrating a MAC to PHY interface according to IEEE Std 802.3™-2005 in relation to the OSI Reference Model Layers 400. The MAC 410 is part of the data link layer 402. The PHY 420 is part of the physical layer 404. The interface 430 between the MAC 410 and the PHY 420 is also part of the physical layer 404.
Various 10 Gigabit/second interfaces may be used between the MAC 410 and the PHY 420. For example, a 10 Gigabit Interface Media Independent Interface (XGMII) in which each sixty-four bit block consists of two consecutive sets of thirty-two data bits with a corresponding 4 bits of controls may be used. The thirty-two data bits and 4 control bits are communicated over 4 lanes in which each lanes carries an octet of data and an associated control bit. 4 lanes are provided for data to be transmitted on the attached media. An independent 4 lanes are provided for data received on the attached media.
Another interface that may be used between the MAC 410 and the PHY 420 is a 10 Gigabit Attachment Unit Interface (XAUI) in which each sixty-four bit block consists of two consecutive sets of four 8B/10B codewords, 8 bits of data and 2 control bits. Still another interface that may be used between the MAC 410 and the PHY 420 is a high speed serial electrical interface for 10 Gb/s small form-factor pluggable transceiver (XFP) modules (XFI) in which each sixty-four bit block consists of one 64B/66B codeword, 64 bits of data and 2 control bits.
10 Gb/s communication between the MAC 410 and the PHY 420 is specified as operating at a fixed clock frequency corresponding to the nominal 10 Gb/s bit rate. Independent transmit and receive data paths are provided between the MAC 410 and the PHY 420. Data is communicated in data frames that begin with a preamble <preamble> and start of frame delimiter <sfd> and end with an end of frame delimiter <efd>. Data within each data frame is communicated in 64 bit code blocks. An inter-frame <inter-frame> period during which no frame data activity occurs separates successive data frames. The inter-frame period can vary in length.
PHYs connected to a 10 Gb/s capable MAC may be required to support the 10 Gb/s MAC data rate. A PHY that is connected to physical media that provides less than a 10 Gb/s data rate may be required to use inter-frame period idle control characters to compensate for the difference in data rates, such as in the mechanism provided by Section 46.1.3, Rate of Operation, of IEEE Std 802.3™-2005 for XGMII. The PHY may buffer one complete frame of incoming data to transmit a data frame to the MAC at the 10 Gb/s MAC data rate. The PHY may buffer more than one complete frame of outgoing data received from the MAC at the 10 Gb/s MAC data rate. A data frame may be up to sixteen kilobytes of data for Ethernet systems. Thus a PHY that is connected to physical media that provides less than a 10 Gb/s data rate may need a significant amount of buffer memory.
In view of the foregoing, it would be useful if the buffer memory requirements could be reduced for a PHY that is connected to physical media that provides less than a 10 Gb/s data rate.